Performance Evaluation of Ring Counter using Gated Clock

Minimizing Power dissipation is one of the major concerns in the VLSI industry.Due the rapid growth in technology, there is a tremendous reduction in the chip size. Minimum power consumption has become a priority.In this paper, we propose a low power design techniquefor Ring counter using gated cloc...

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Bibliographic Details
Published inInternational journal of engineering & technology (Dubai) Vol. 7; no. 3.12; p. 701
Main Authors Mala S, Pushpa, S P, Bharath, ., Anjum, Kumar, Aniket, Kundu, Debolina
Format Journal Article
LanguageEnglish
Published 20.07.2018
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Summary:Minimizing Power dissipation is one of the major concerns in the VLSI industry.Due the rapid growth in technology, there is a tremendous reduction in the chip size. Minimum power consumption has become a priority.In this paper, we propose a low power design techniquefor Ring counter using gated clock.In this paper, we demonstrate the working of ring counter using gated clock.The results are illustrated in Xilinx. The simulation results and the synthesis outputis shown.  
ISSN:2227-524X
2227-524X
DOI:10.14419/ijet.v7i3.12.16458