(Invited) Monolithic Integration of Zinc Tin Oxide Electronics

• Published in: Meeting abstracts (Electrochemical Society) Vol. MA2020-01; no. 23; p. 1328
• Main Authors: Son, Youngbae, Allemang, Chris, Frost, Brad, Zhao, Yunkai, Peterson, Rebecca L.
• Format: Journal Article
• Language: English
• Published: 01.05.2020
• ISSN: 2151-2043; 2151-2035
• DOI: 10.1149/MA2020-01231328mtgabs

Oxide semiconductors’ unique properties – a wide bandgap, reasonably high electron mobility, and ease of bulk and thin film preparation – make them prime material candidates for a variety of electronic devices. In this talk, I will describe my group’s recent demonstration of amorphous zinc tin oxide ( a- ZTO) electronic devices for thin film monolithic integration of comparatively high voltage (2 to 100 V) power electronics on top of low voltage (V DD ~ 1.2V) state-of-the-art silicon CMOS. We use an in-air solution process to synthesize a -ZTO semiconductor thin films. The resulting bottom-gate, top-contact transistors have field effect mobility of 8.3 cm 2 V -1 s -1 and enhancement-mode behavior with turn-on near zero volts. By controlling ink dilution, we form homogeneous, amorphous channel layers less than 10 nm thick. When passivated with ozone-based atomic layer deposition of Al 2 O 3 to stabilize the exposed top surface of the active layer, the transistors have excellent bias stress stability and sharp sub-threshold turn-on [1,2]. Next, we successfully integrated our thin film a -ZTO transistors directly on top of silicon finFET CMOS in the back end of line. The ZTO device fabrication process is fully compatible with finFET CMOS: after ZTO transistor formation, both the bottom silicon transistors and top a -ZTO transistors function well, with no degradation in performance. To expand the range of devices available for ZTO circuit design, we then developed several other device technologies. Using the Gibbs free energy of oxide formation and ionic radii of the bottom metal thin films as selection criteria, we chose metal contact layers and device structure to form multiple types of components – MISFETs, MESFETs, Schottky diodes, and resistive memory devices [3–5] – using one integrated fabrication process. With these devices, we demonstrate three applications. First, we make full-wave rectifiers that can harvest wireless power from commercial 13.56 MHz RFID signals and use the resulting d.c. voltage to switch underlying low voltage silicon finFETs. Second, we make logic inverters with low switching voltage window and single-transistor amplifiers with high gain by combining a depletion-mode MESFET device as a load and enhancement-mode MISFET devices as the drive transistor. Third, by incorporating a gate-drain offset into the MISFET design, we increase the TFT blocking voltage to above 100 V, enabling future 3-D monolithic integration of high voltage / low voltage interface power electronic circuits on top of silicon CMOS ICs [6]. Thanks to G. A. Torres Sevilla and M. M. Hussain for providing silicon CMOS, N. Dasgupta and C. Huber for depositing alumina with ozone, and W. Hu, J. Li and J. Miller for help with TFT fabrication. This work was supported by SPAWAR through DARPA Young Faculty Award N66001-14-1-4046. Any opinions, findings, conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of DARPA or SPAWAR. Y.S. was supported in part by the Kwanjeong Educational Foundation. Portions of the work were performed in the Lurie Nanofabrication Facility, which is supported by the University of Michigan’s College of Engineering. [1] C. R. Allemang, R. L. Peterson, IEEE Electron Device Lett. 2019 , 40 , 1120; [2] Y. Son, A. Liao, R. L. Peterson, J Mater Chem C 2017 , 5 , 8071; [3] Y. Son, R. L. Peterson, in 2017 75th Annu. Device Res. Conf. DRC , 2017 , pp. 1–2; [4] Y. Son, R. L. Peterson, Adv. Funct. Mater. 2019 , 29 , 1806002; [5] Y. Son, B. Frost, Y. Zhao, R. L. Peterson, Nat. Electron. 2019 , 2 , 540; [6] C. Allemang, R. L. Peterson, in 2017 75th Annu. Device Res. Conf. DRC , IEEE, South Bend, IN, 2017 , pp. 1–2.