A Sub-50-fs rms Jitter Fractional- N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 59; no. 3; pp. 677 - 689
Main Authors Ye, Zonglin, Geng, Xinlin, Xiao, Yao, Xie, Qian, Wang, Zheng
Format Journal Article
LanguageEnglish
Published 01.03.2024
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3339679