Low-latency machine learning FPGA accelerator for multi-qubit-state discrimination

• Main Authors: Gautam, Pradeep Kumar, Kalipatnapu, Shantharam, H, Shankaranarayanan, Singhal, Ujjawal, Lienhard, Benjamin, Singh, Vibhor, Thakur, Chetan Singh
• Format: Journal Article
• Language: English
• Published: 04.07.2024
• Subjects: Computer Science - Hardware Architecture; Computer Science - Learning; Physics - Quantum Physics
• DOI: 10.48550/arxiv.2407.03852

Measuring a qubit state is a fundamental yet error-prone operation in quantum computing. These errors can arise from various sources, such as crosstalk, spontaneous state transitions, and excitations caused by the readout pulse. Here, we utilize an integrated approach to deploy neural networks onto field-programmable gate arrays (FPGA). We demonstrate that implementing a fully connected neural network accelerator for multi-qubit readout is advantageous, balancing computational complexity with low latency requirements without significant loss in accuracy. The neural network is implemented by quantizing weights, activation functions, and inputs. The hardware accelerator performs frequency-multiplexed readout of five superconducting qubits in less than 50 ns on a radio frequency system on chip (RFSoC) ZCU111 FPGA, marking the advent of RFSoC-based low-latency multi-qubit readout using neural networks. These modules can be implemented and integrated into existing quantum control and readout platforms, making the RFSoC ZCU111 ready for experimental deployment.