PLA driver selection an analytic approach
Few integrated circuit design tools support the rapid exploration of the design space across performance alternatives. Such a tool must rely on extensive analysis of fundamental design issues, to provide the basis for this exploration. These detailed analyses are summarized as simple "rules-of-...
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Published in | Proceedings of the 22nd ACM/IEEE Design Automation Conference pp. 798 - 802 |
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Main Authors | , |
Format | Conference Proceeding |
Language | English |
Published |
Piscataway, NJ, USA
IEEE Press
01.06.1985
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Series | ACM Conferences |
Subjects | |
Online Access | Get full text |
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Summary: | Few integrated circuit design tools support the rapid exploration of the design space across performance alternatives. Such a tool must rely on extensive analysis of fundamental design issues, to provide the basis for this exploration. These detailed analyses are summarized as simple "rules-of-thumb." A more flexible class of design tools can use these to generate integrated circuit designs with more desirable performance.
This paper describes the detailed analysis of the PLA driver selection problem. Rules-of-thumb which summarize these results for nMOS, are developed and applied to a large CPU design project currently underway at Berkeley. A maximum critical driver delay improvement of 46% was realized. |
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ISBN: | 0818606355 9780818606359 |
DOI: | 10.5555/317825.317998 |