Hardware acceleration of gate array layout

• Published in: Proceedings of the 22nd ACM/IEEE Design Automation Conference pp. 359 - 366
• Main Authors: Spira, Philip M., Hage, Carl
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 01.06.1985
• Series: ACM Conferences
• Subjects: Hardware > Electronic design automation > Physical design (EDA) > Partitioning and floorplanning; Hardware > Electronic design automation > Physical design (EDA) > Placement; Hardware > Electronic design automation > Physical design (EDA) > Wire routing; Hardware > Very large scale integration design > Application-specific VLSI designs
• ISBN: 0818606355; 9780818606359
• DOI: 10.5555/317825.317913

In this paper we describe the hardware and software of a system which we have implemented to accelerate the physical design of gate arrays. In contrast to nearly all other reported approaches, our approach to hardware acceleration is to augment a single-user host workstation with a general-purpose microprogrammable slave processor having a large private memory. One or more such slaves can be attached. We have implemented placement improvement on the system, achieving a 20 x speedup vs. a high-level host implementation. We give performance results, which are comparable to those reported elsewhere for mainframe implementations.