ARGO aging-aware GPGPU register file allocation

• Published in: Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis pp. 1 - 9
• Main Authors: Namaki-Shoushtari, Majid, Rahimi, Abbas, Dutt, Nikil, Gupta, Puneet, Gupta, Rajesh K.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 29.09.2013
• Series: ACM Conferences
• Subjects: Computer systems organization > Architectures > Parallel architectures > Single instruction, multiple data; register file; power-gating; aging; NBTI; GPGPU
• ISBN: 1479914177; 9781479914173
• DOI: 10.5555/2555692.2555722

State-of-the-art general-purpose graphic processing units (GPGPUs) implemented in nanoscale CMOS technologies offer very high computational throughput for highly-parallel applications using hundreds of integrated on-chip resources. These resources are stressed during application execution, subjecting them to degradation mechanisms such as negative bias temperature instability (NBTI) that adversely affect their reliability. To support highly parallel execution, GPGPUs contain large register files (RFs) that are among the most highly stressed GPGPU components; however we observe heavy underutilization of RFs (on average only 46%) for typical general-purpose kernels. We present ARGO, an Aging-awaRe GPGPU RF allOcator that opportunistically exploits this RF underutilization by distributing the stress throughout RF. ARGO achieves proper leveling of RF banks through deliberated power-gating of stressful banks. We demonstrate our technique on the AMD Evergreen GPGPU architecture and show that ARGO improves the NBTI-induced threshold voltage degradation by up to 43% (on average 27%), that yields improving RFs static noise margin up to 46% (on average 30%). Furthermore, we estimate a simultaneous reduction in leakage power of 54% by providing sleep states for unused banks.