Quality-configurable memory hierarchy through approximation special session

• Published in: Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion pp. 1 - 2
• Main Authors: Shoushtari, Majid, Rahmani, Amir M., Dutt, Nikil
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 15.10.2017
• Series: ACM Other Conferences
• Subjects: Hardware; Hardware > Integrated circuits; Hardware > Integrated circuits > Semiconductor memory; Hardware > Integrated circuits > Semiconductor memory > Dynamic memory; approximate computing; cross-layer design; memory hierarchy
• ISBN: 1450351840; 9781450351843
• DOI: 10.1145/3125501.3125525

The memory subsystem is a major contributor to the overall performance and energy consumption of embedded computing platforms. The emergence of "killer" applications such as data-intensive recognition, mining, and synthesis (RMS) applications puts even more stress on the memory subsystem and exacerbates its energy consumption. Traditional mechanisms to ensure data integrity deploy overdesign (e.g., redundancy and error detection/correction) and/or guard-banding that consumes a significant part of the energy consumed in the memory subsystem. We explore opportunities for energy efficiency by exploiting the intrinsic tolerance of a vast class of approximate computing applications to some level of error in the on-chip memory hierarchy. We present two exemplars outlining the typical software and hardware mechanisms that are required for different components in the memory hierarchy, implemented in varying technologies such as SRAM and STT-MRAM.