Reconfigurable Packet FEC Architecture for Mobile Networks

This paper presents a reconfigurable hardware architecture of Forward Error Correction (FEC) coding algorithm for mobile networks, with high throughput on Field Programmable Gate Array (FPGA). The design can be reconfigured for different message length and different generator number, the encoder and...

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Bibliographic Details
Published inMobile Web and Intelligent Information Systems pp. 115 - 121
Main Author El-Medany, Wael M.
Format Book Chapter
LanguageEnglish
Published Cham Springer International Publishing
SeriesLecture Notes in Computer Science
Subjects
FEC
FPGA
Mobile networks
VHDL
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Summary:This paper presents a reconfigurable hardware architecture of Forward Error Correction (FEC) coding algorithm for mobile networks, with high throughput on Field Programmable Gate Array (FPGA). The design can be reconfigured for different message length and different generator number, the encoder and decoder has been described using VHDL (VHSIC Hardware Description Language). The decoder has the ability to detect and correct different types and different numbers of errors based on the message length and the length of redundant data. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level.
ISBN:9783319231433
331923143X
ISSN:0302-9743
1611-3349
DOI:10.1007/978-3-319-23144-0_11