Memory-Centric Communication Architecture for Reconfigurable Computing

This paper presents a memory-centric communication architecture for a reconfigurable array of processing elements, which reduces the communication overhead by establishing a direct communication channel through a memory between the array and other masters in the system. Not to increase the area cost...

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Bibliographic Details
Published inReconfigurable Computing: Architectures, Tools and Applications pp. 400 - 405
Main Authors Chang, Kyungwook, Choi, Kiyoung
Format Book Chapter
LanguageEnglish
Published Berlin, Heidelberg Springer Berlin Heidelberg 2010
SeriesLecture Notes in Computer Science
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Summary:This paper presents a memory-centric communication architecture for a reconfigurable array of processing elements, which reduces the communication overhead by establishing a direct communication channel through a memory between the array and other masters in the system. Not to increase the area cost too much, we do not use a multi-port memory, but divide the memory into multiple memory units, each having a single port. The masters and the memory units have one-to-one mapping through a simple crossbar switch, which switches whenever data transfer is needed. Experimental results show that the proposed architecture achieves 76% performance improvement over the conventional architecture.
ISBN:9783642121326
3642121322
ISSN:0302-9743
1611-3349
DOI:10.1007/978-3-642-12133-3_40