Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching

• Published in: High Performance Embedded Architectures and Compilers pp. 247 - 261
• Main Authors: Grannaes, Marius, Jahre, Magnus, Natvig, Lasse
• Format: Book Chapter
• Language: English
• Published: Berlin, Heidelberg Springer Berlin Heidelberg
• Series: Lecture Notes in Computer Science
• ISBN: 9783642115141; 3642115144
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-642-11515-8_19

This paper presents a low complexity table-based approach to delta correlation prefetching. Our approach uses a table indexed by the load address which stores the latest deltas observed. By storing deltas rather than full miss addresses, considerable space is saved while making pattern matching easier. The delta-history can predict repeating patterns with long periods by using delta correlation. In addition, we propose L1 hoisting which is a technique for moving data from the L2 to the L1 using the same underlying table structure and partial matching which reduces the spatial resolution in the delta stream to expose more patterns. We evaluate our prefetching technique using the simulator framework used in the Data Prefetching Championship. This allows us to use the original code submitted to the contest to fairly evaluate several alternate prefetching techniques. Our prefetcher technique increases performance by 87% on average (6.6X max) on SPEC2006.