Intellectual Property (IP) Integration Approach for Data-Flow Parallel Embedded Systems

• Published in: e-Infrastructure and e-Services for Developing Countries pp. 298 - 307
• Main Authors: Chana, Anne Marie, Quinton, Patrice
• Format: Book Chapter
• Language: English
• Published: Berlin, Heidelberg Springer Berlin Heidelberg
• Series: Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
• Subjects: data-flow model; flexible component; IP reused; multi-frequency system; parallelism; Polyhedral model; SoC
• ISBN: 9783642411779; 3642411770
• ISSN: 1867-8211; 1867-822X
• DOI: 10.1007/978-3-642-41178-6_31

The growing complexity of new chips and the time to market constraints require fundamental changes in the systems design approach. Systems on chip (SoC) based on reused components called intellectual property (IP) has become an absolute necessity to the embedded systems companies in order to remain competitive. This paper focuses on the IP reuse to design parallel and multi-frequency applications. The flexible parallel components described by the Alpha functional language are modelled and assembled using a scheduling method which combines the synchronous data-flow principle of balance equations and, the polyhedral scheduling technique. Our approach allows a flexible component to be modelled and, a full system to be assembled and synthesized by combining the component hardware descriptions with automatically generated wrappers. We discuss the relationship of this approach with stream languages, latency-insensitive design, and multidimensional data-flow systems.