Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems

Processor-based digital systems are increasingly being used in safety-critical environments. To meet the associated safety requirements, these systems are usually characterized by a certain degree of redundancy. This paper proposes a concept to introduce a redundant processor on demand by using the...

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Bibliographic Details
Published inApplied Reconfigurable Computing pp. 96 - 111
Main Authors Dörr, Tobias, Sandmann, Timo, Schade, Florian, Bapp, Falco K., Becker, Jürgen
Format Book Chapter
LanguageEnglish
Published Cham Springer International Publishing
SeriesLecture Notes in Computer Science
Subjects
Dynamic redundancy
Fail-operational system
Fallback processor
Graceful degradation
Multiprocessor system-on-chip
Partial reconfiguration
Simplex architecture
Soft-core processor
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Summary:Processor-based digital systems are increasingly being used in safety-critical environments. To meet the associated safety requirements, these systems are usually characterized by a certain degree of redundancy. This paper proposes a concept to introduce a redundant processor on demand by using the partial reconfiguration capability of modern FPGAs. We describe a possible implementation of this concept and evaluate it experimentally. The evaluation focuses on the fault handling latency and the resource utilization of the design. It shows that an implementation with 32 KiB of local processor memory handles faults within 0.82 ms and, when no fault is present, consumes less than 46% of the resources that a comparable static design occupies.
ISBN:3030172260
9783030172268
ISSN:0302-9743
1611-3349
DOI:10.1007/978-3-030-17227-5_8