Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler

This paper presents a new environment for exploring and optimizing VLIW architectures for multimedia applications. The environment consists of a generic VLIW architecture, in which virtually all characteristics can be changed, and an assembler with the corresponding parameterized scheduler based on...

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Published inArchitecture of Computing Systems - ARCS 2007 pp. 254 - 267
Main Authors Payá-Vayá, Guillermo, Martín-Langerwerf, Javier, Taptimthong, Piriya, Pirsch, Peter
Format Book Chapter
LanguageEnglish
Published Berlin, Heidelberg Springer Berlin Heidelberg
SeriesLecture Notes in Computer Science
Subjects
Design Space Exploration
Functional Unit
List Schedul
List Schedule
Register File
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Abstract This paper presents a new environment for exploring and optimizing VLIW architectures for multimedia applications. The environment consists of a generic VLIW architecture, in which virtually all characteristics can be changed, and an assembler with the corresponding parameterized scheduler based on an enhanced version of the list scheduling algorithm. A novel partitioned register file architecture is proposed and analyzed with this environment. This is performed using a highly time consuming task of the H.264 video decoder application. Performance improvements of up to 67% can be achieved when running this application on different architecture configurations.
AbstractList This paper presents a new environment for exploring and optimizing VLIW architectures for multimedia applications. The environment consists of a generic VLIW architecture, in which virtually all characteristics can be changed, and an assembler with the corresponding parameterized scheduler based on an enhanced version of the list scheduling algorithm. A novel partitioned register file architecture is proposed and analyzed with this environment. This is performed using a highly time consuming task of the H.264 video decoder application. Performance improvements of up to 67% can be achieved when running this application on different architecture configurations.
Author Pirsch, Peter
Martín-Langerwerf, Javier
Payá-Vayá, Guillermo
Taptimthong, Piriya
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Copyright Springer Berlin Heidelberg 2007
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DOI 10.1007/978-3-540-71270-1_19
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StartPage 254
SubjectTerms Design Space Exploration
Functional Unit
List Schedul
List Schedule
Register File
Title Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler
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