CROB: Implementing a Large Instruction Window through Compression

• Published in: Transactions on High-Performance Embedded Architectures and Compilers III pp. 115 - 134
• Main Authors: Latorre, Fernando, Magklis, Grigorios, González, Jose, Chaparro, Pedro, González, Antonio
• Format: Book Chapter
• Language: English
• Published: Berlin, Heidelberg Springer Berlin Heidelberg 2011
• Series: Lecture Notes in Computer Science
• Subjects: Average Speedup; Circular Buffer; Logical Register; Register File; Segment Size
• ISBN: 3642194478; 9783642194474
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-642-19448-1_7

Current processors require a large number of in-flight instructions in order to look for further parallelism and hide the increasing gap between memory latency and processor cycle time. These in-flight instructions are typically stored in centralized structures called reorder buffer (ROB), which is a centerpiece to handle precise exceptions and recover a safe state in the event of a branch misprediction. However, this structure is becoming so big that it is difficult to fit it in the power budget of future processors designs. In this paper we propose a novel ROB microarchitecture named CROB (Compressed ROB) that can compress ROB entries and therefore give the illusion of having a larger virtual ROB than the number of ROB entries. The performance study of CROB shows a tremendous benefit, with an average speedup of 20% and 12% for a 128-entry and 256-entry ROB respectively. For some benchmark categories such as SpecFP2000, speedup raise up to 30%.