A TSE based design for MMSE and QRD of MIMO systems based on ASIP

• Published in: 高技术通讯（英文版） Vol. 29; no. 2; pp. 166 - 173
• Main Authors: FENG Xuelin, SHI Jinglin, CHEN Yang, FU Yanlu, ZHANG Qineng, XIAO Feng
• Format: Journal Article
• Language: English
• Published: School of Computer Science and Technology,University of Chinese Academy of Sciences,Beijing 100049,P.R.China 01.06.2023; Beijing Sylincom Technology Co.,Ltd.,Beijing 100190,P.R.China%Beijing Key Laboratory of Mobile Computing and Pervasive Device,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100080,P.R.China%Beijing Sylincom Technology Co.,Ltd.,Beijing 100190,P.R.China; Beijing Key Laboratory of Mobile Computing and Pervasive Device,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100080,P.R.China
• Subjects: very; minimum mean-square error(MMSE); application specific instruction set pro-cessor(ASIP); instruction set architecture(ISA); multi-input and multi-output(MIMO); single instruction multiple data(SIMD); QR decomposition(QRD); Taylor series expansion(TSE)
• ISSN: 1006-6748
• DOI: 10.3772/j.issn.1006-6748.2023.02.007

A Taylor series expansion(TSE)based design for minimum mean-square error(MMSE)and QR decomposition(QRD)of multi-input and multi-output(MIMO)systems is proposed based on application specific instruction set processor(ASIP),which uses TSE algorithm instead of resource-consuming reciprocal and reciprocal square root(RSR)operations.The aim is to give a high per-formance implementation for MMSE and QRD in one programmable platform simultaneously.Further-more,instruction set architecture(ISA)and the allocation of data paths in single instruction multi-ple data-very long instruction word(SIMD-VLIW)architecture are provided,offering more data par-allelism and instruction parallelism for different dimension matrices and operation types.Meanwhile,multiple level numerical precision can be achieved with flexible table size and expansion order in TSE ISA.The ASIP has been implemented to a 28 nm CMOS process and frequency reaches 800 MHz.Experimental results show that the proposed design provides perfect numerical precision within the fixed bit-width of the ASIP,higher matrix processing rate better than the requirements of 5G system and more rate-area efficiency comparable with ASIC implementations.