Design and implementation of instruction-driven and data-driven self-reconfigurable cell array

• Published in: 高技术通讯（英文版） Vol. 29; no. 1; pp. 31 - 40
• Main Authors: SHAN Rui, XIA Xinyuan, YANG Kun, CUI Xinyue, LIAO Wang, GAO Xu
• Format: Journal Article
• Language: English
• Published: School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,P.R.China%School of Safety Science and Engineering,Xi'an University of Science and Technology,Xi'an 710054,P.R.China 01.03.2023
• Subjects: instruction-driven; configurable computing; data-driven; cell array
• ISSN: 1006-6748
• DOI: 10.3772/j.issn.1006-6748.2023.01.004

The reconfigurable chip, which integrates the advantages of high performance, high flexibility, high parallelism, low power consumption, and low cost, has achieved rapid development and wide application. Generally, the control part and the computing part of algorithm is accelerated based on different reconfigurable architectures, but it is difficult to obtain overall performance improvement. For improving efficiency of reconfigurable structure both for the control part and the computing part, a hybrid of instruction-driven and data-driven self-reconfigurable cell array is proposed. On instruc-tion-driven mode, processing element ( PE) works like a reduced instruction set computer ( RSIC) machine, which is mainly for the control part of algorithm. On data-driven mode, data is calculated by flowing between the preconfigured PEs, which is mainly for the computing of algorithm. For verif-ying the efficiency of architecture, some high-efficiency video coding ( HEVC) video compression algorithms are implemented on the proposed architecture. The proposed architecture has been imple-mented on Xilinx FPGA Virtex UltraScale VU440 develop board. The same circuitry is able to run at 75 MHz. Compared with the architecture that only supports instruction-driven, the proposed archi-tecture has better calculation efficiency.