Research and design of matrix operation accelerator based on reconfigurable array

• Published in: 高技术通讯（英文版） Vol. 30; no. 2; pp. 128 - 137
• Main Authors: DENG Junyong, ZHANG Pan, JIANG Lin, XIE Xiaoyan, DENG Jingwen
• Format: Journal Article
• Language: English
• Published: School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,P.R.China%School of Computer Science and Technology,Xi'an University of Science and Technology,Xi'an 710054,P.R.China%School of Computer,Xi'an University of Posts and Telecommunications,Xi'an 710121,P.R.China 01.06.2024
• Subjects: matrix multiplication; recommender system(RS); matrix factorization(MF); array processor; recon-figurable
• ISSN: 1006-6748
• DOI: 10.3772/j.issn.1006-6748.2024.02.003

In the case of massive data,matrix operations are very computationally intensive,and the mem-ory limitation in standalone mode leads to the system inefficiencies.At the same time,it is difficult for matrix operations to achieve flexible switching between different requirements when implemented in hardware.To address this problem,this paper proposes a matrix operation accelerator based on reconfigurable arrays in the context of the application of recommender systems(RS).Based on the reconfigurable array processor(APR-16)with reconfiguration,a parallelized design of matrix opera-tions on processing element(PE)array is realized with flexibility.The experimental results show that,compared with the proposed central processing unit(CPU)and graphics processing unit(GPU)hybrid implementation matrix multiplication framework,the energy efficiency ratio of the ac-celerator proposed in this paper is improved by about 35×.Compared with blocked alternating least squares(BALS),its the energy efficiency ratio has been accelerated by about 1×,and the switc-hing of matrix factorization(MF)schemes suitable for different sparsity can be realized.