Challenges in achieving sub-100 nm MOSFETs

• Published in: Proceedings - International Conference on Wafer Scale Integration
• Main Author: Tasch, Al F
• Format: Journal Article
• Language: English
• Published: 01.01.1997
• ISSN: 1063-2204

The continued scaling of the MOS transistor to smaller feature sizes has been the prime factor in the remarkable advancements in integrated circuits over the past 25-30 years. This is due to the fact that successively smaller devices have allowed continued rapid improvements in the level of integration and performance. While sub-100 nm MOSFETs have been built in the laboratory, it is by no means straightforward to extend MOSFETs below 100 nm such that continued notable (cost justified) improvements in integrated circuit performance, reliability, and manufacturability will be maintained. This talk focuses on the major challenges that are encountered in designing and building MOSFETs with sub 100 nm gate lengths. The requirements on the structure and its component parts are examined, and potential solutions are discussed. Solutions to some of the challenges and obstacles will require revolutionary approaches and tremendous research and development resources and talent.