A zero-IF single-chip transceiver for up to 22Mb/s QPSK 802.11b wireless LAN
A zero-intermediate single-chip transceiver was proposed for upto 22Mb /s quadrature phase shift keying 802.11b wireless local area networks (LAN). The proposed architecture consists of three external filters, two cascaded power amplifiers, external voltage controlled oscillators (VCO) and synthesiz...
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Published in | Digest of technical papers - IEEE International Solid-State Circuits Conference |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
01.01.2001
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Online Access | Get full text |
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Summary: | A zero-intermediate single-chip transceiver was proposed for upto 22Mb /s quadrature phase shift keying 802.11b wireless local area networks (LAN). The proposed architecture consists of three external filters, two cascaded power amplifiers, external voltage controlled oscillators (VCO) and synthesizers. A differential low noise amplifier (LNA) is used to reduce LO-RF feed-through and switching noise from digital circuits. The measurement of the automatic signal settling for a sinusoidal input was shown. It was found that a fully-on-chip VCO with tuning range between 1.2 and 1.25GHz is doubled to generate the 2.45GHz LO signal. |
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Bibliography: | SourceType-Scholarly Journals-2 ObjectType-Feature-2 ObjectType-Conference Paper-1 content type line 23 SourceType-Conference Papers & Proceedings-1 ObjectType-Article-3 |
ISSN: | 0193-6530 |