Optimized Low Power Dual Edge Triggered Flip-flop with Speed Enhancement

• Published in: International journal of image, graphics and signal processing Vol. 15; no. 1; p. 50
• Main Authors: Shilpa, K C, Lakshminarayana, C
• Format: Journal Article
• Language: English
• Published: Hong Kong Modern Education and Computer Science Press 01.02.2022
• Subjects: Circuits; Consumption; Flip-flops; Power consumption; Sense amplifiers; Signal processing; Simulation; Switching; Transistors
• ISSN: 2074-9074; 2074-9082
• DOI: 10.5815/ijigsp.2022.01.05

This paper gives a novel low-power approach with pulse generating circuits using dual edge triggered flip-flops. By doing so, flip-flop might operate at 1.2Volts, with the novel quick latch and conditional precharging. This paper aims at a new proposed low power dual edge triggered flip-flop with speed enhancement to achieve low power consumption with a shorter delay in power usage, hence, it is well suited for low-power digital system applications. The new proposed low power dual edge triggered flip-flop also aims at comparison with the three DETFF, Static Output Controlled Discharge Flip-Flop (SCDFF), Dual Edge Triggered Static Pulsed Flip-flop (DETSPFF), and Pervious work on Dual Edge Triggered flip-flop, proves to achieves with reduction in numbers of transistors in the stack and increases the number of charge-paths results in a faster operational speed. According to simulation on Spectre simulator, it has been observed that total power consumption of proposed flip flop at 0.67 switching activity is 30.16 % and 27.36 % less than that of previous arts DSPFF and SCDFF respectively. Clock-gated sense-amplifier is incorporated to reduce power consumption at low switching activity. The simulation is done using Cadence tool with 45nm standard CMOS technology.