Full CMP integration of CVD TiN damascene sub-0.1-mum metal gate devices for ULSI applications

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-m...

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Published inIEEE transactions on electron devices Vol. 48; no. 8; pp. 1816 - 1821
Main Authors Ducroquet, F, Achard, H, Coudert, F, Previtali, B, Lugand, J-F, Ulmer, L, Farjot, T, Gobil, Y, Heitzmann, M, Tedesco, S, Nier, M E, Deleonibus, S
Format Journal Article
LanguageEnglish
Published 01.08.2001
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Summary:Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-mum gate transistors up to 0.6-mm(2) capacitors). CVD TiN film as a damascene gate electrode shows excellent properties for MOS performances and gate oxide integrity even on ultrathin gate oxide (2-nm SiO(2))
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9383
DOI:10.1109/16.936712