Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements

High-speed, low latency convolutional turbo codes require a parallel decoder architecture. To maximise the gain in speed, the interleaver also should have a parallel structure. Here, a class of optimum parallel interleavers regarding the access to storage elements is presented. They combine regulari...

Full description

Saved in:
Bibliographic Details
Published inElectronics letters Vol. 38; no. 5; p. 1
Main Authors Giulietti, A, van der Perre, L, Strum, M
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 28.02.2002
Subjects
Collisions
Data transfer (computers)
Decoders
Gain
High speed
Optimization
Regularity
Turbo codes
Online AccessGet full text

Cover

More Information
Summary:High-speed, low latency convolutional turbo codes require a parallel decoder architecture. To maximise the gain in speed, the interleaver also should have a parallel structure. Here, a class of optimum parallel interleavers regarding the access to storage elements is presented. They combine regularity (easy implementation) with no latency in data transfer between the decoder module and intrinsic/extrinsic values memories, and show excellent BER performance.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:0013-5194
1350-911X