Full-parallel architecture for turbo decoding of product codes

A full-parallel architecture for turbo decoding, which achieves ultrahigh data rates, when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed-Solomon component codes. The major advantage of this architecture is...

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Bibliographic Details
Published inElectronics letters Vol. 42; no. 18; p. 1
Main Authors Jégo, C, Adde, P, Leroux, C
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 31.08.2006
Subjects
Architecture
Data storage
Decoders
Decoding
Error correcting codes
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Summary:A full-parallel architecture for turbo decoding, which achieves ultrahigh data rates, when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed-Solomon component codes. The major advantage of this architecture is that, it enables the memory blocks between all half-iterations to be removed. Moreover, the latency of the turbo decoder is strongly reduced. The proposed architecture opens the way to numerous applications, such as optical transmission and data storage. In particular, the block turbo decoding architecture can support optical transmission at data rates above 10 Gbit/s.
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ISSN:0013-5194
1350-911X