Parallel pipelined histogram architectures

Proposed is a unique cell histogram architecture, which will process k data items in parallel to compute 2^sup q^ histogram bins per time step. An array of m/2^sup q^ cells computes an m-bin histogram with a speed-up factor of k; k ≥ 2 makes it faster than current dual-ported memory implementations....

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Bibliographic Details
Published inElectronics letters Vol. 47; no. 20; p. 1
Main Authors Cadenas, J, Sherratt, R S, Huerta, P
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 29.09.2011
Subjects
Architecture
Arrays
Bins
Histograms
Storage
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Summary:Proposed is a unique cell histogram architecture, which will process k data items in parallel to compute 2^sup q^ histogram bins per time step. An array of m/2^sup q^ cells computes an m-bin histogram with a speed-up factor of k; k ≥ 2 makes it faster than current dual-ported memory implementations. Furthermore, simple mechanisms for conflict-free storing of the histogram bins into an external memory array are discussed.
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ISSN:0013-5194
1350-911X