Differential CMOS edge-triggered flip-flop with clock-gating

A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. The PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when the switching activity of the input signal is <0.65. Power reduction can be a...

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Bibliographic Details
Published inElectronics letters Vol. 38; no. 1; p. 1
Main Authors Xia, Y, Almaini, A E A
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 03.01.2002
Subjects
Chains
Circuit design
Clocks
CMOS
Flip-flops
Idling
Simulation
Switching
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Summary:A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. The PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when the switching activity of the input signal is <0.65. Power reduction can be as high as 86% when the input is idle.
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ISSN:0013-5194
1350-911X