RNS-based implementation of 8 × 8 point 2D-DCT over field-programmable devices

A new implementation of an 8 x 8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS), is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that, the RNS implementation of the 2D-DCT over field-programmable logic...

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Bibliographic Details
Published inElectronics letters Vol. 39; no. 1; p. 1
Main Authors Fernández, P G, Lloris, A
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 09.01.2003
Subjects
Algorithms
Binary systems
Devices
Equivalence
Microprocessors
Residue number systems
Transforms
Two dimensional
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Summary:A new implementation of an 8 x 8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS), is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that, the RNS implementation of the 2D-DCT over field-programmable logic devices leads to a 129% throughput improvement over the equivalent binary system.
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ISSN:0013-5194
1350-911X