Micropower CMOS S&H circuit for ambient intelligence applications

A novel sample and hold (S&H) circuit is presented, based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 μm double-poly CMOS technology. The quiescent power consumption...

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Bibliographic Details
Published inElectronics letters Vol. 41; no. 17; p. 1
Main Authors López-Martín, A J, De La Cruz, C A, Ugalde, X, Carvajal, R G, Ramirez-Angulo, J
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 18.08.2005
Subjects
Ambient intelligence
Circuits
CMOS
Electric potential
Power consumption
Silicon
Slew rate
Voltage
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Summary:A novel sample and hold (S&H) circuit is presented, based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 μm double-poly CMOS technology. The quiescent power consumption is only 80 mW, using a dual supply voltage of ±1.35 V. The S&H occupies 0.075 mm^sup 2^ of silicon area.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
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ISSN:0013-5194
1350-911X