Reliability Increasing Method Using a SEC-DED Hsiao Code to Cache Memories, Implemented with FPGA Circuits

In this paper we will apply a Hsiao code to the cache level of a memory hierarchy to increase the reliability of the memory. We have selected the Hsiao code from the category of SEC-DED (Single Error Correction Double Error Detection) codes. For correction of a single-bit error we use, a check bits...

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Bibliographic Details
Published inJournal of Computer Science and Control Systems Vol. 4; no. 2; p. 59
Main Authors Novac, Ovidiu, Sztrik, Janos, Vari-Kakas, Stefan, Kim, Che-Soong
Format Journal Article
LanguageEnglish
Published Oradea University of Oradea 01.10.2011
Subjects
Cache
Categories
Circuits
Control systems
Error correction
Error detection
Field programmable gate arrays
Generators
Hierarchies
Reliability
Studies
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Summary:In this paper we will apply a Hsiao code to the cache level of a memory hierarchy to increase the reliability of the memory. We have selected the Hsiao code from the category of SEC-DED (Single Error Correction Double Error Detection) codes. For correction of a single-bit error we use, a check bits generator circuit, a syndrome generator and a syndrome decoder. Implementation of SEC-DED code in the cache is made with FPGA Xilinx circuits. [PUBLICATION ABSTRACT]
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:1844-6043
2067-2101