Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 39; no. 9; pp. 1536 - 1543
Main Authors HAZUCHA, Peter, KARNIK, Tanay, BORKAR, Shekhar, WALSTRA, Steven, BLOECHEL, Bradley A, TSCHANZ, James W, MAIZ, Jose, SOUMYANATH, Krishnamurthy, DERMER, Gregory E, NARENDRA, Siva, DE, Vivek
Format Journal Article
LanguageEnglish
Published New York, NY Institute of Electrical and Electronics Engineers 01.09.2004
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Radiation hardening
Single event upset
radiation hardened latch
Soft error
Index Terms-Error control coding
Latch circuit
Neutron beam
Error correcting code
CMOS integrated circuits
Microprocessor
Reliability
soft error rate
soft errors
Fault tolerant system
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More Information
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2004.831449