OPTIMIZING SOC TEST RESOURCES USING DUAL SEQUENCES

In this paper, we propose a new data structure called dual sequences to represent SOC test schedules. Dual sequences are used together with a simulated annealing based procedure to optimize the SOC test application time and tester resources. The problems we consider are generation of optimal test sc...

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Bibliographic Details
Published inVLSI-SOC pp. 181 - 196
Main Authors Zou, Wei, Chu, Chris C. N., Reddy, Sudhakar M., Pomeranz, Irith
Format Book Chapter
LanguageEnglish
Published United States Kluwer Academic Publishers 2006
Springer US
SeriesIFIP International Federation for Information Processing
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Summary:In this paper, we propose a new data structure called dual sequences to represent SOC test schedules. Dual sequences are used together with a simulated annealing based procedure to optimize the SOC test application time and tester resources. The problems we consider are generation of optimal test schedules for SOCs and minimizing tester memory and test channels. Results of experiments conducted on ITC’02 benchmark SOCs show the effectiveness of the proposed method.
Bibliography:The work of W. Zou and S. M. Reddy supported in part by NSF Grant CCR-0097005 and SRC Grant 001-TJ-949. Work of I. Pomeranz supported in part by NSF Grant CCR-0098091 and by SRC Grant 2001-TJ-950.
ISBN:9780387334028
0387334025
ISSN:1571-5736
DOI:10.1007/0-387-33403-3_12