Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique

• Published in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Vol. 6951; pp. 143 - 151
• Main Authors: Huang, Henry X. F., Shen, Steven R. S., Kuo, James B.
• Format: Book Chapter
• Language: English
• Published: Germany Springer Berlin / Heidelberg 2011; Springer Berlin Heidelberg
• Series: Lecture Notes in Computer Science
• Subjects: BFS; CBLPRP; Dual-threshold CMOS; GDSPOM; MTCMOS; Power Optimization
• ISBN: 9783642241536; 3642241530
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-642-24154-3_15

This paper describes a straightforward cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing high-speed low-power SOC applications using MTCMOS technique. The CBLPRP methodology is based on the cell swapping priority depending on the total leakage power reduction for a cell changing from LVT type to HVT type. Experimental results show that by employing CBLPRP Methodology on the ISCAS benchmark circuits, a 10-20% reduction in the leakage power consumption could be achieved as compared to the one using the GDSPOM technology.