FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder

• Published in: Intelligent Information Technology pp. 344 - 353
• Main Authors: Mohanty, Saraju P., Kumara C., Renuka, Nayak, Sridhara
• Format: Book Chapter Conference Proceeding
• Language: English
• Published: Berlin, Heidelberg Springer Berlin Heidelberg 01.01.2004; Springer
• Series: Lecture Notes in Computer Science
• Subjects: Applied sciences; Artificial intelligence; Computer science; control theory; systems; Digital Right Management; Digital Watermark; Exact sciences and technology; Finite State Machine; Learning and adaptive systems; Linear Feedback Shift Register; Watermark Algorithm; Access control; Multimedia; Content management; Pseudorandom number; Stéganography; Field programmable gate array; Encryption; Low power; Real time; Shift register; Intellectual property; Safety; Cryptography; Watermark; Artificial intelligence; Structural analysis; Digital watermarking
• ISBN: 9783540241263; 3540241264
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-540-30561-3_36

Both encryption and digital watermarking techniques need to be incorporated in a digital rights management framework to address different aspects of content management. While encryption transforms original multimedia object into another form, digital watermarking leaves the original object intact and recognizable. The objective is to develop low power, real time, reliable and secure watermarking systems, which can be achieved through hardware implementations. In this paper, we present an FPGA based implementation of an invisible spatial domain watermarking encoder. The watermarking encoder consists of a watermark generator, watermark insertion module, and a controller. Most of the invisible watermarking algorithms available in the literature and also the algorithm implemented in this paper insert pseudorandom numbers to host data. Therefore, we focus on the structural design aspects of watermarking generator using linear feedback shift register. We synthesized the prototype watermarking encoder chip using Xilinx FPGA.