A 4.6‐GHz low‐phase‐noise differential common‐gate Clapp VCO with simplified common‐mode biasing

• Published in: Microwave and optical technology letters Vol. 59; no. 7; pp. 1676 - 1680
• Main Authors: Din, Amad Ud, Nghia Nguyen, Tai, Phan, Huu Nhan, Nguyen, Khac Vu, Lee, Jong‐Wook
• Format: Journal Article
• Language: English
• Published: New York Wiley Subscription Services, Inc 01.07.2017
• Subjects: Clapp; CMOS; Electric potential; Phase noise; Power consumption; Transconductance; VCO; Voltage controlled oscillators
• ISSN: 0895-2477; 1098-2760
• DOI: 10.1002/mop.30602

We present a new differential Clapp voltage‐controlled oscillator (VCO) suitable for low‐voltage scaled‐down CMOS technology. For loss compensation, the Clapp VCO uses a common‐gate topology that provides higher transconductance than that of the conventional common‐drain configuration. To provide reliable start‐up condition for the Clapp VCO, a small inductor is added at the gate of a transistor in the common‐gate configuration. The new configuration also simplifies DC biasing while providing a suitable common‐mode point for varactor tuning. All of these features allow the Clapp VCO to operate under low‐voltage and low‐power conditions. The fabricated Clapp VCO using 0.18‐μm RFCMOS achieves an excellent phase noise performance of −121 dBc/Hz at a 1 MHz offset from 4.6 GHz. Under a supply voltage of 1.0 V and a power consumption of 4.2 mW, the figure‐of‐merit (FOM) is −188 dBc/Hz.