Implementation of a FIR Filter on a Partial Reconfigurable Platform

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the re...

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Bibliographic Details
Published inKnowledge-Based Intelligent Information and Engineering Systems pp. 108 - 115
Main Authors Lee, Hanho, Choi, Chang-Seok
Format Book Chapter Conference Proceeding
LanguageEnglish
Published Berlin, Heidelberg Springer Berlin Heidelberg 2006
Springer
SeriesLecture Notes in Computer Science
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Summary:This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.
ISBN:3540465421
9783540465423
3540465359
9783540465355
ISSN:0302-9743
1611-3349
DOI:10.1007/11893011_14