Model Checking Timed Systems with Urgencies

• Published in: Automated Technology for Verification and Analysis pp. 67 - 81
• Main Authors: Hsiung, Pao-Ann, Lin, Shang-Wei, Chen, Yean-Ru, Huang, Chun-Hsian, Yeh, Jia-Jen, Sun, Hong-Yu, Lin, Chao-Sheng, Liao, Hsiao-Win
• Format: Book Chapter Conference Proceeding
• Language: English
• Published: Berlin, Heidelberg Springer Berlin Heidelberg 2006; Springer
• Series: Lecture Notes in Computer Science
• Subjects: Applied sciences; Computer science; control theory; systems; Exact sciences and technology; Software; Software engineering; Branching temporal logic CTL; State space method; Modeling; Timed system; Real time system; Tree automaton; Program verification; Boarded computer; Timed automata; Semantics; Static analysis; Observer; Model checking
• ISBN: 9783540472377; 3540472371
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/11901914_8

Computation tree logic (CTL) model checkers either allow modeling of only lazy semantics in the timed system model or consider at most a simple as soon as possible semantics. However, the design of real-time systems requires different types of urgencies, which have been modeled by several urgency variants of the timed automata model. Except for the IF toolset that model checks timed automata with urgency against observers, the urgency variants of timed automata have not yet been used for verifying the satisfaction of CTL properties in real-time systems. This work is targeted at proposing a zone-based urgency semantics that is time-reactive and at model checking timed automata models that have been extended with such urgency semantics for delayable and eager transition types. Interactions among these different types of transition urgencies are also investigated. The proposed verification methods were implemented in the SGM CTL model checker and applied to real-time and embedded systems. Several experiments, comparing the state space sizes produced by SGM with that by the IF toolset, show that SGM produces much smaller state-spaces.