0.18-μm CMOS equalization techniques for 10-Gb/s fiber optical communication links

• Published in: IEEE transactions on microwave theory and techniques Vol. 53; no. 11; pp. 3509 - 3519
• Main Authors: MAENG, Moonkyun, BIEN, Franklin, HUR, Youngsik, KIM, Hyoungsoo, CHANDRAMOULI, Soumya, GEBARA, Edward, LASKAR, Joy
• Format: Conference Proceeding Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 01.11.2005
• Subjects: Applied sciences; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); CMOS; Delay; Delay lines; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Equalization; Equalizers; Exact sciences and technology; Fiber optics; Integrated circuits; Integrated circuits by function (including memories and processors); Links; Optical fibers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Integrated optics; LC circuit; Data transmission; Continuous time; Equalizer; Output stage; Implementation; feed-forward equalizer (FFE); Complementary MOS technology; Multiplier; 10-Gb/s; Optical fiber communication; Delay time; Optical bus; Separator circuit; Delayed time; 0.18-μm CMOS; Optical fiber; High rate transmission; Optical links; Arithmetic circuit; delay-locked loop (DLL); Channel capacity; Output circuit; finite impulse response (FIR) filter; Equalization; Active inductive peaking; nonreturn to zero (NRZ); input/output (I/O) interconnection; LC ladder; multimode fiber (MMF); Integrated circuit; Modal dispersion; Delay line
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2005.857108

Limitations in data transmission caused by modal dispersion in fiber-optic links can be significantly improved using equalization techniques. In this paper, two different equalizer implementation approaches are proposed to extend the transmission capacities of existing fiber-optic links. The building blocks of the equalizer including a multiplier cell, a delay line, and an output buffer stage are fully integrated on a 0.18- mu m CMOS process. For the continuous-time tap-delay implementation, a passive LC delay line and an active inductance peaking delay line are compared for performance against process variation, as well as power consumption. In addition, a delay-locked loop is proposed to counter delay variations caused by changes in the process corner. A 10-Gb/s nonreturn-to-zero signal is received after transmission through a 500-m multimode-fiber channel, and the signal impairment due to the differential modal delay is successfully compensated using both feed-forward equalizers.