4-Mb MOSFET-selected μtrench phase-change memory experimental chip

• Published in: IEEE journal of solid-state circuits Vol. 40; no. 7; pp. 1557 - 1565
• Main Authors: BEDESCHI, Ferdinando, BEZ, Roberto, OTTOGALLI, Federica, PELLIZZER, Fabio, PIROVANO, Agostino, RESTA, Claudio, TORELLI, Guido, TOSI, Marina, BOFFINO, Chiara, BONIZZONI, Edoardo, CASSIODORO BUDA, Egidio, CASAGRANDE, Giulio, COSTA, Lucio, FERRARO, Marco, GASTALDI, Roberto, KHOURI, Osama
• Format: Conference Proceeding Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 01.07.2005
• Subjects: Access time; Applied sciences; Arrays; Chips (memory devices); CMOS; Current distribution; Design. Technologies. Operation analysis. Testing; Durability; Electric potential; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; MOSFETs; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Storage and reproduction of information; Transistors; Performance evaluation; sense amplifier; Memory devices; High performance; Access time; MOSFET; Phase-Change Memories; Cascode connection; Amplifier; Pulse code modulation; nonvolatile memories; Flash memory; Non volatile memory; Complementary MOS technology; Integrated circuit; Cascode bitline biasing; Current distribution
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2005.847531

A mu trench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18- mu m CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.