Technology and reliability constrained future copper interconnects - Part II: Performance implications

This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in Part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly depe...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 49; no. 4; pp. 598 - 604
Main Authors Kapur, Pawan, Chandra, Gaurav, McVittie, James P, Saraswat, Krishna C
Format Journal Article
LanguageEnglish
Published 01.04.2002
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Summary:This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in Part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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ISSN:0018-9383
DOI:10.1109/16.992868