A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

• Published in: IEEE journal of solid-state circuits Vol. 47; no. 1; pp. 107 - 116
• Main Authors: KIM, Jung-Sik, CHI SUNG OH, RYU, Jang-Woo, PARK, Kiwon, SANG KYU KANG, KIM, So-Young, KIM, Hoyoung, BANG, Jong-Min, CHO, Hyunyoon, JANG, Minsoo, HAN, Cheolmin, LEE, Jung-Bae, LEE, Hocheol, JOO SUN CHOI, JUN, Young-Hyun, LEE, Donghyuk, HYONG RYOL HWANG, HWANG, Sooman, NA, Byongwook, MOON, Joungwook, KIM, Jin-Guk, PARK, Hanna
• Format: Conference Proceeding Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 2012; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bandwidth; Blocking; Channels; Chips; Circuits; Correlation; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Packages; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Stacking; Performance evaluation; through-silicon vias; Die; Stacking; Random access memory; CMOS memory circuits; Correlation method; Non volatile memory; Interconnection; Electronic packaging; Integrated circuit; DRAM chips; Silicon; CMOS integrated circuits; CMOS memory integrated circuits; Dynamic random access memory; Via hole
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2011.2164731

A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period refresh scheme is applied to reduce self refresh current with minimum chip size burden. Stacking of 2 dies with 7.5 [Formula Omitted] diameter and 40 [Formula Omitted] pitch TSVs has been fabricated and tested, which results in 76% overall package yield without difference in performances between top and bottom die.