A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches

• Published in: VLSI Design and Test Vol. 892; pp. 521 - 537
• Main Authors: Manivannan, T. S., Srinivasan, Meena
• Format: Book Chapter
• Language: English
• Published: Singapore Springer Singapore Pte. Limited 2019; Springer Singapore
• Series: Communications in Computer and Information Science
• ISBN: 9811359490; 9789811359491
• ISSN: 1865-0929; 1865-0937
• DOI: 10.1007/978-981-13-5950-7_44

Pulsed-latches provide high performance with low power consumption by taking the advantages of both flip-flops and latches and thus, they are targeted in implementing different kinds of memory devices in various applications. One such memory device is the register files, which is traditionally being realized using SRAMs. To implement n READ/WRITE multi-ports in SRAM register file design, the transistors that forms READ/WRITE ports must be replicated n times. Thus, there exist a proportionality between the number of transistors required per cell and the number of READ/WRITE ports per cell. This relationship is completely eliminated in the proposed pulsed-latches based register file design. The proposed pulsed-latches requires only 10 transistors per cell for any number of READ/WRITE ports. The proposed pulsed-latches based multiport register files consumes low power, area efficient and performs multi-read and multi-write operations. Hence, to implement n READ/WRITE ports in pulsed-latches based register files, n individual non-overlapping pulses are required, thereby making the number of transistors required per cell to be unchanged. These register files showed significant decrease in area as well as power consumption when compared to the SRAM based register files. An 8-bit(1X8), 64-bit(8X8), 128-bit(16X8) and a 256-bit(32X8) 4-READ and 2-WRITE (4R2W) pulsed-latches based multiport register files were designed and simulated in cadence 180 nm technology.