CPLD-Based Synthesis with Transformation of State Codes

• Published in: Logic Synthesis for VLSI-Based Combined Finite State Machines Vol. 922; pp. 215 - 248
• Main Authors: Kawecka, Elżbieta, Mazurkiewicz, Małgorzata, Titarenko, Larysa, Barkalov, Alexander, Mielcarek, Kamil
• Format: Book Chapter
• Language: English
• Published: Switzerland Springer International Publishing AG 2022; Springer International Publishing
• Series: Lecture Notes in Electrical Engineering
• ISBN: 9783031160264; 3031160266
• ISSN: 1876-1100; 1876-1119
• DOI: 10.1007/978-3-031-16027-1_7

TheTransformation ofstate codes chapter is devoted to the hardware reductionHardware reduction based on transformation of state codes into the codes of classes of PES. The chapter starts from the complete state transformation. The method is applied for CFSMs implemented with either homogenous or heterogeneous CPLDs. These methods are applied if outcome of the optimal state assignmentState assignmentoptimal is far from optimal. It is shown how to combine this approach with other methods of structural decompositionDecompositionstructural. Next, the CFSMs with the partial state transformationTransformationpartial are analysed. It is proposed to use two codes for classes of PES. It can be done due to a wide fan-in of PALProgrammable Array Logic (PAL)macrocellsMacrocell. Next, this approach is combined with other methods of structural decomposition. The same is done for CFSMs with PLA-basedProgrammable Logic Array (PLA) macrocells. Next, it is shown how to optimize hardware sharing EMBs and macrocells to implement the same systems of Boolean functionsBooleanfunctions. At last, different methods of object transformationObject transformation are discussed for heterogeneous CPLDs. All proposed methods target reducing the numbers of product termsProduct term in systems of Boolean functions representing CFSM circuits. The examples of synthesis are given for majority of proposed CFSM models.