A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS

This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an inte...

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Published inIEEE journal of solid-state circuits Vol. 40; no. 9; pp. 1932 - 1939
Main Authors PENGFEI ZHANG, DER, Lawrence, GOWDER, Sujatha, HART, Siegfried, HUYNH, Lam, NGUYEN, Thai, RAZAVI, Behzad, DAWEI GUO, SEVER, Isaac, BOURDI, Taoufik, LAM, Christopher, ZOLFAGHARI, Alireza, CHEN, Jess, GAMBETTA, Douglas, BAOHONG CHENG
Format Conference Proceeding Journal Article
LanguageEnglish
Published New York, NY Institute of Electrical and Electronics Engineers 01.09.2005
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Summary:This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54 degree /1.1 degree for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2005.848182