Area array solder interconnection technology for the three-dimensional silicon cube

• Published in: Electronic Components & Technology Conference. Proceedings. pp. 1174-1178. 1995 pp. 1174 - 1178
• Main Authors: Howell, Wayne J, Brouillette, Donald W, Korejwa, Josef W, Sprogis, Edmund J, Yankee, Sally J, Wursthorn, John M
• Format: Journal Article Conference Proceeding
• Language: English
• Published: 01.01.1995
• Subjects: Ceramic materials; Composite structures; Integrated circuits; Microprocessor chips; Substrates; Thermal expansion; Thermal gradients; Three dimensional
• ISSN: 0569-5503

Area array solder interconnection technology has been successfully implemented on three-dimensional (3-D) silicon cubes. The 3-D semiconductor components are fabricated using silicon-cube technology. Multiple integrated circuit chips are stacked, laminated and interconnected, creating a fast ultra-high-density component. Critical to realizing these advantages is the use of area array solder-bump interconnection, with its high I/O density, to first-level packaging. Several technology challenges have been addressed in successfully and reliably implementing area array interconnections. The 3-D ultra-high-density component, with its composite structure, is large, can have different thermal expansion coefficients in the two axes defining the solder-bump interconnection plane and dynamic thermal gradients throughout the structure. This paper presents the silicon-cube technology, discusses the inherent area array solder-bump interconnection challenges and reviews the implementation and qualification results.