Successive Approximation Register (SAR) ADC with Improved Timing Control Logic for Neural Recording Front-End IC

This paper presents an improved control logic for successive approximation register (SAR) analog to digital converter (ADC). To eliminate the racing problem, the improved SAR timing controller using additional "AND" gate array is proposed. In the conventional SAR logic, a shift-register ba...

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Bibliographic Details
Published inInternational Information Institute (Tokyo). Information Vol. 18; no. 5(A); p. 1687
Main Authors Song, Haryong, Seok, Changho, Kim, Hyunho, Im, Seunghyun, Ko, Hyoungho
Format Journal Article
LanguageEnglish
Published Koganei International Information Institute 01.05.2015
Subjects
Approximation
Circuits
Logic
Mathematical analysis
Racing
Registers
Sampling
Time measurements
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Summary:This paper presents an improved control logic for successive approximation register (SAR) analog to digital converter (ADC). To eliminate the racing problem, the improved SAR timing controller using additional "AND" gate array is proposed. In the conventional SAR logic, a shift-register based timing controller is widely used. However, the racing problem between the falling edge of asynchronous set signal and rising edge of comparator update signal can be occurred. The proposed circuit achieves the timing margin of half clock duration, and eliminates the racing problem in conventional SAR logic. The 12-bit SAR ADC using the proposed circuit is also presented. Simulation results of the designed 12-bit SAR ADC show that the efficient number of bits (ENOB) is 11.01-bit when operating at 4 kS/s sampling rate.
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ISSN:1343-4500
1344-8994