A 10 b 120 Msample/s time-interleaved analog-to-digital converter with digital background calibration

A 10 b 120 Msample/s time-interleaved analog-to -digital converter (ADC) was studied. This time-interleaved pipelined ADC uses digital background calibration to overcome the effects of mismatch errors without affecting the signal spectrum, without a calibration signal, and without a front-rank sampl...

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Published inDigest of technical papers - IEEE International Solid-State Circuits Conference pp. 132 - 133+436
Main Authors Jamal, Shafiq M, Fu, Daihong, Hurst, Paul J, Lewis, Stephen H
Format Journal Article
LanguageEnglish
Published 01.01.2002
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Summary:A 10 b 120 Msample/s time-interleaved analog-to -digital converter (ADC) was studied. This time-interleaved pipelined ADC uses digital background calibration to overcome the effects of mismatch errors without affecting the signal spectrum, without a calibration signal, and without a front-rank sample-and-hold amplifier (SHA). Time interleaving can increase the speed of an ADC, but mismatch erros usually limit the overall accuracy.
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ISSN:0193-6530