Hybrid Dynamic Branch Prediction to Reduce Destructive Aliasing

This paper presents a prediction structure with a Hybrid Dynamic Branch Prediction (HDBP) scheme which decreases the number of stalls. In the application, a branch history register is dynamically adjusted to produce more unique index values of pattern history table (PHT). The number of stalls is als...

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Bibliographic Details
Published in한국정보통신학회논문지 Vol. 23; no. 12; pp. 1734 - 1737
Main Author Jongsu Park(박종수)
Format Journal Article
LanguageEnglish
Published 한국정보통신학회 01.12.2019
Subjects
전자/정보통신공학
Dynamic Prediction
Branch History
Branch
Prediction Accuracy
Online AccessGet full text
ISSN2234-4772
2288-4165
DOI10.6109/jkiice.2019.23.12.1734

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Summary:This paper presents a prediction structure with a Hybrid Dynamic Branch Prediction (HDBP) scheme which decreases the number of stalls. In the application, a branch history register is dynamically adjusted to produce more unique index values of pattern history table (PHT). The number of stalls is also reduced by using the modified gshare predictor with a long history register folding scheme. The aliasing rate decreased to 44.1% and the miss prediction rate decreased to 19.06% on average compared with the gshare branch predictor, one of the most popular two-level branch predictors. Moreover, Compared with the gshare, an average improvement of 1.28% instructions per cycle (IPC) was achieved. Thus, with regard to the accuracy of branch prediction, the HDBP is remarkably useful in boosting the overall performance of the superscalar processor. KCI Citation Count: 0
Bibliography:http://jkiice.org
ISSN:2234-4772
2288-4165
DOI:10.6109/jkiice.2019.23.12.1734