Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structur...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 17; no. 3; pp. 401 - 410
Main Author Jin-Young Choi
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.06.2017
Subjects
전기공학
ESD protection
RF ICs
parasitic bipolar transistor
diode protection device
mixed-mode simulation
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Summary:In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the VDD and VSS buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements. KCI Citation Count: 1
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2017.17.3.401