Compact Capacitance Model of L-Shape Tunnel Field-Effect Transistors for Circuit Simulation

• Published in: Journal of Information and Communication Convergence Engineering, 19(4) Vol. 19; no. 4; pp. 263 - 268
• Main Authors: Yun Seop Yu, Faraz Najam
• Format: Journal Article
• Language: English
• Published: 한국정보통신학회JICCE 2021; 한국정보통신학회
• Subjects: 전자/정보통신공학; Inverter; Capacitance; Tunnel filed-effect transistor; Compact model; Verilog-A
• ISSN: 2234-8255; 2234-8883
• DOI: 10.6109/jicce.2021.19.4.263

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed,those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET(LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of PandL-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was alsodeveloped to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation resultsusing the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) devicesimulator. The current–voltage characteristics and capacitance–voltage characteristics of N and P-LTFETs were consistent forall operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and PLTFETsin series were verified with the TCAD mixed-mode simulation results. KCI Citation Count: 0