An FPGA Implementation of High-Speed Flexible 27-Mbps 8-StateTurbo Decoder

• Published in: ETRI journal Vol. 29; no. 3; pp. 363 - 370
• Main Authors: Choi, Duk-Gun, Kim, Min-Hyuk, Jeong, Jin-Hee, Jung, Ji-Won, Bae, Jong-Tae, Choi, Seok-Soon, Yun, Young
• Format: Journal Article
• Language: Korean
• Published: 한국전자통신연구원 01.06.2007; ETRI
• Subjects: 전자/정보통신공학; dual-path processing; radix-4 algorithm; FPGA; Coset mapping
• ISSN: 1225-6463; 2233-7326

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half-rate turbo decoder designed for binary quadrature phase-shift keying (B/QPSK) modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implement the proposed scheme on a field-programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.